FPGA硬件电子琴电路设计实验报告

FPGA硬件电子琴电路设计实验报告

FPGA硬件电子琴电路设计实验报告

其功能仿真波形和时序仿真波形分别如下:

3.输入音阶发生器程序并命名为,保存与工程相同的文件夹中。

PreClk<=1'b0;

Count4<=Count4+4'b1; end end

always@(posedge PreClk)begin if(Count11>=11'h7FF) begin

Count11<=Tone;

FullSpkS<=1'b1; end else begin PreClk<=1'b1;

Count4<=1;end

else begin

Count11<=Count11+11'b1; FullSpkS<=0; end end

always@(posedge FullSpkS)begin

Count2<=~Count2; if(Count2==1'b1) SpkS<=1'b1;

else SpkS<=1'b0; end

Module ToneTaba (Index,Code,High,Tone); input[3:0] Index; output[3:0] Code; output High; output[10:0] Tone; reg[3:0] Code=0; reg High=0; reg[10:0] Tone=0; always begin

case(Index) 4'b0000 :begin Tone<=11'b; Code<=4'b0000;High<=1'b0;end//2047 4'b0001 :begin Tone<=11'b001; Code<=4'b0001;High<=1'b0;end//773

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