TMS320 Ti官方原版数据手册

TMS320系列DSP Ti官方原版数据手册

TMS320 Ti官方原版数据手册

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TMS320DM642

Video/ImagingFixed-PointDigitalSignalProcessor

SPRS200J–JULY2002–REVISEDAUGUST2005

1

1.1

TMS320DM642Video/ImagingFixed-PointDigitalSignalProcessor

Features

MemorySpace

EnhancedDirect-Memory-Access(EDMA)Controller(64IndependentChannels)10/100Mb/sEthernetMAC(EMAC)–IEEE802.3Compliant

–MediaIndependentInterface(MII)

–8IndependentTransmit(TX)Channelsand1Receive(RX)Channel

ManagementDataInput/Output(MDIO)ThreeConfigurableVideoPorts

–ProvidingaGluelessI/FtoCommonVideoDecoderandEncoderDevices

–SupportsMultipleResolutions/VideoStdsVCXOInterpolatedControlPort(VIC)

–SupportsAudio/VideoSynchronizationHost-PortInterface(HPI)[32-/16-Bit]

32-Bit/66-MHz,3.3-VPeripheralComponentInterconnect(PCI)Master/SlaveInterfaceConformstoPCISpecification2.2

MultichannelAudioSerialPort(McASP)–EightSerialDataPins

–WideVarietyofI2SandSimilarBitStreamFormat

–IntegratedDigitalAudioI/FTransmitterSupportsS/PDIF,IEC60958-1,AES-3,CP-430Formats

Inter-IntegratedCircuit(I2CBus )

TwoMultichannelBufferedSerialPortsThree32-BitGeneral-PurposeTimersSixteenGeneral-PurposeI/O(GPIO)PinsFlexiblePLLClockGeneratorIEEE-1149.1(JTAG)Boundary-Scan-Compatible

548-PinBallGridArray(BGA)Package(GDKandZDKSuffixes),0.8-mmBallPitch548-PinBallGridArray(BGA)Package(GNZandZNZSuffixes),1.0-mmBallPitch0.13-µm/6-LevelCuMetalProcess(CMOS)3.3-VI/O,1.2-VInternal(-500)

3.3-VI/O,1.4-VInternal(A-500,A-600,-600,-720)

High-PerformanceDigitalMediaProcessor–2-,1.67-,1.39-nsInstructionCycleTime–500-,600-,720-MHzClockRate–Eight32-BitInstructions/Cycle–4000,4800,5760MIPS

–FullySoftware-CompatibleWithC64x VelociTI.2 ExtensionstoVelociTI

AdvancedVery-Long-Instruction-Word(VLIW)TMS320C64x DSPCore

–EightHighlyIndependentFunctionalUnitsWithVelociTI.2 Extensions:

SixALUs(32-/40-Bit),EachSupportsSingle32-Bit,Dual16-Bit,orQuad8-BitArithmeticperClockCycle

TwoMultipliersSupportFour16x16-BitMultiplies(32-BitResults)perClock

CycleorEight8x8-BitMultiplies(16-BitResults)perClockCycle

–Load-StoreArchitectureWithNon-AlignedSupport

–6432-BitGeneral-PurposeRegisters–InstructionPackingReducesCodeSize–AllInstructionsConditionalInstructionSetFeatures

–Byte-Addressable(8-/16-/32-/64-BitData)–8-BitOverflowProtection–Bit-FieldExtract,Set,Clear

–Normalization,Saturation,Bit-Counting–VelociTI.2 IncreasedOrthogonalityL1/L2MemoryArchitecture

–128K-Bit(16K-Byte)L1PProgramCache(DirectMapped)

–128K-Bit(16K-Byte)L1DDataCache(2-WaySet-Associative)

–2M-Bit(256K-Byte)L2UnifiedMappedRAM/Cache(FlexibleRAM/CacheAllocation)

Endianess:LittleEndian,BigEndian64-BitExternalMemoryInterface(EMIF)–GluelessInterfacetoAsynchronousMemories(SRAMandEPROM)and

SynchronousMemories(SDRAM,SBSRAM,ZBTSRAM,andFIFO)

1024M-ByteTotalAddressableExternal

Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdocument.

WindowsisaregisteredtrademarkofMicrosoftCorporation.I2CBusisatrademarkofPhilipsElectronicsN.V..

PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.

Copyright©2002–2005,TexasInstrumentsIncorporated

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