全志A13原理图(Q8)

5

4

3

2

1

COVER BLOCK POWER TREE

D

MPU

PMU AXP209

LCD

G-Sensor USB0 OTG USB1 WIFI

TP

LAYOUT:ACIN、BAT、IPSOUT输入或输出线,从PMU管脚处就要保证尽量粗。 ACIN(5V)2A

D

Interconnect Network,and Power Driven

DCDC2

1V2@1.6A 1V2@1.2A 3V3@30mA 3V@200mA 3V3@400mA 3V3@200mA

CPU VDD CORE VDD RTC AVCC WIFI

AXP209

USBVBUS (5V-900mA)

Battery charger/detect

DCDC3 LDO1 LDO2 LDO3

DDR3

NAND

KEY CSI SPEAKER

CARD

HEADPHONE MIC MOTOR BAT(4.2V)

GPIO ASSIGNMENT CPU C

Define

Function

PB0 PB1 PB2 PB3 PB4 PB10 PB15 PB16 PB17 PB18

TWI0_SCK TWI0_SDA PWM0 GPIO-OUT NC GPIO-OUT TWI1_SCK TWI1_SDA TWI2_SCK TWI2_SDA

TWI0 LCD TP-WAKE-RST CSI-STY TWI1

IPSOUT 5V-2A

LDO4

MOTOR

C

TWI2

SY8008B SD0-DET-N USB0-VBUSDET USB0-IDDET UART-TX UART-RX MT-EN PA-SHDN TP-INT USB0-DRV Function

SY8008B

SY7208 SY7201 AP3031KTR SY7201 AP3019KTR

PG0 PG1 PG2 PG3 B

INPUT GPIO-IN GPIO-IN UART-TX UART-RX GPIO-OUT GPIO-OUT EINT GPIO-OUT Define

3V3@1A 特别提醒: 1: PG0/ PG1/ PG2这三个PIN脚只具有INPUT/中断/专有功能 2: PMU的GPIO0/1/2/3这四个PIN脚只做GPIO-OUTPUT功能 3: PG10/PG11/PG12这三个PIN脚的功能不可改变

1V6@1A DRAM LP3992-18B5F AP1231B18ZRM LP3992-28B5F AP1231B28ZRM

PG4 PG9 PG10 PG11 PG12 PMU

CARD NAND G-SENSOR TP MOTOR

5V@1A USB OTG

9V9@1A LCD BL

10V4@1A B

LCD AVDD

GPIO0 GPIO1 GPIO2 GPIO3

GPIO-OUT GPIO-OUT GPIO-OUT GPIO-OUT

LCD-PWR LCD-BL-EN CSI-PWR-EN CSI-RST

1V8@1A CSI-CORE

2V8@1A CSI-IO

REVISION HISTORY

Revision APP3_PAD_DDR3_V1_10 A

Description version 1.10

Date

Drawn CPL

Checked

Approved A

Title APP3_PAD_DDR3 Size A3 Date: 5 4 3 2

Document Name COVER Sheet 1

Rev 1 of 6

全志A13原理图(Q8)

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