module shuzizhong(clk50m,pause,clr,led0,led1,led2,led3,led4,led5); parameter weishu=8;

input clk50m;

input pause;

input clr;

output[weishu-1:0]led5;

output[weishu-1:0]led4;

output[weishu-1:0]led3;

output[weishu-1:0]led2;

output[weishu-1:0]led1;

output[weishu-1:0]led0;

wire isstop;

wire zero;

switch #(8) switchstop(clk50m,pause,isstop);

switch #(8) switchzero(clk50m,clr,zero);

reg[18:0] counter_100hz;

wire clk100;

assign clk100=counter_100hz[18];

always @(posedge clk50m)

begin if(!isstop)

begin if(counter_100hz==19'b1111010000100100000)

counter_100hz<=0;

else counter_100hz=counter_100hz+1;

end end

reg[3:0] hs0;

reg hscarry0;

reg[3:0] hs1;

reg hscarry1;

reg[3:0] sec0;

reg seccarry0;

reg[3:0] sec1;

reg seccarry1;

reg[3:0] minu0;

reg miucarry0;

reg[3:0] minu1;

always@(posedge clk100 or posedge zero)

begin if(zero)

begin hs0<=0;

hscarry0<=0;

end

else if(clk100==1)

begin if(hs0==9) begin hs0<=0;hscarry0<=1;end

else begin hs0<=hs0+1;hscarry0<=0;end

end